Ic 74ls138 Logic Diagram. Dc triggered from active high or active low logic inputs input clamp diodes low power dissipation compensated for vcc and temperature variations figure 1 is a functional block diagram of the ls123. Each one shot has two inputs one active low and one active high which allow both leading or trailing edge triggering.
To designate the different gates on the same chip. Led runner with 74ls163 under led circuits. Ic 74ls138 logic diagram digital electronics and logic design unit i combinational logic design demux decoder ic 74138 ic 74154 dmux tree implementation of sop and pos using mux dmux comparators parity generators and checker priority realize full adder and subtractor using a basic gates and b universal gates half adder and full adder circuits is explained with their truth tables.
Logic diagram 5 231 fast and ls ttl data sn5474ls138 functional description the ls138 is a high speed 1 of 8 decoderdemultiplexer fabricated with the low power schottky barrier diode process.
Sn5474ls138 1 of 8 decoder demultiplexer low power schottky j suffix ceramic case 620 09 n suffix plastic case 648 08 16 1 16 1 ordering information sn54lsxxxj ceramic sn74lsxxxn plastic sn74lsxxxd soic 16 1 d suffix soic case 751b 03 logic symbol vcc pin 16 gnd pin 8 15 14 13 12 11 10 9 12 3 456 123 a0 a1 a2 e o0o1o2o3 o4o5 o6o7 7 logic diagram a2 a1 a0 e1 e2 e3 o7 o6. Demultiplexers in multiple variations. Add ic remove ic. The actual purpose of this chip is designed for demultiplexing or in machine language we can say as a decoding device.