Block Diagram Xilinx. The next step is to add some ip from the catalog. The serdes from two adjacent blocks m aster and slave can be cascaded to make an 8 bit block.
In the block diagram double click the axi dma block. The data path consists of independent dma interfaces for the transmit and receive paths. Click add ip.
Search for zynqand then double click the zynq ultrascale mpsocfrom the ip search results.
Zynq 7000s devices feature a single core arm cortex a9 processor mated with 28nm artix 7 based programmable logic representing the lowest cost entry point to the scalable zynq 7000 platform. This ip allows slicing out one individual bit or a number of bits from a bit vector or bus. Project wizard settings. The din width value specifies the input bus width.