Block Diagram 8259. It reduces the software and real time overhead generated due to handling multilevel priority interrupts. The block diagram of 8259 is as shown in the figure below.
It can be programmed either work in 8085 or in 8086 microprocessors. The 8259s can be cascaded to accept a maximum of 64 interrupts. D7 d0 is connected to microprocessor data bus d7 d0 ad7 ad0.
Three registers irr isr and imr v.
Wr the write input connects to write strobe signal of microprocessor. It also induces additional features such as level triggered mode buffered mode and automatic end of interrupt mode. Priority resolver pr 8. As the number of 8259 increases interrupt pins up to 64 can be obtained.